Vulnerabilities
Known CPU vulnerabilities and defects, matched by codename.
11 vulnerabilities
| Vulnerability | CPUs | First released | Meaning |
|---|---|---|---|
| Foreshadow / L1 Terminal Fault | 1389 | 04'16 | Speculative reads from the L1 data cache through non-present page table entries, breaking SGX, OS and VMM isolation. |
| Meltdown | 1707 | 04'16 | Rogue data cache load: user code can read kernel memory through speculative execution. |
| Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout) | 1512 | 04'16 | Data in store buffers, fill buffers and load ports leaks across privilege boundaries. |
| Retbleed | 921 | 04'16 | Return instructions are hijacked through the branch target buffer on cores without enhanced IBRS. |
| Special Register Buffer Data Sampling (CrossTalk) | 1065 | 04'16 | RDRAND/RDSEED results leak across cores through a shared staging buffer. |
| Spectre variant 1 (bounds check bypass) | 2637 | 04'16 | Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected. |
| Downfall / Gather Data Sampling | 816 | 2015-Q3 | The AVX gather instruction leaks stale data from internal vector registers. |
| Register File Data Sampling | 295 | 2016-Q3 | Atom-class cores leak stale register file contents. |
| TSX Asynchronous Abort (ZombieLoad v2) | 336 | 2017-Q4 | Aborted TSX transactions leak data from microarchitectural buffers, including on parts that fixed MDS. |
| Reptar | 439 | 2019-Q3 | Redundant instruction prefixes put the front end into an undefined state, allowing privilege escalation or denial of service. |
| Vmin shift instability | 42 | 2022-Q4 | Elevated operating voltage requests degrade 13th/14th generation desktop CPUs over time, causing crashes. Mitigated by microcode 0x12B. |