Intel Server CPU v1.0.3
64-bit Intel Xeon Processor LV 2.80 GHz, 1M Cache, 800 MHz FSB
Metadata
| Property | Value |
|---|---|
| Brand | Xeon |
| Intel name | 64-bit Intel Xeon Processor LV 2.80 GHz, 1M Cache, 800 MHz FSB |
| Codename | Nocona |
| Generation | NetBurst |
| Microarchitecture | NetBurst |
| Performance class | Xeon |
| Segment | Server |
| Released | 2004-Q22004 |
| Status | Discontinued |
| Cores | 1 |
| Base clock | 2.80 GHz |
| Cache | 1 MB L2 Cache |
| Bus | 800 MHz |
| TDP | 55 W |
| Lithography (as published) | 90 nm |
| Transistors | 125 million |
| Die size | 112 mm2 |
| Instruction set | 64-bit |
| Socket | PPGA604PGA604 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v11.0.0(90 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.1.0(SSE2)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel Server CPU v1.0.2 (Xeon 2.40 GHz, 512K Cache, 533 MHz FSB)
Features
- +Intel 64
- +Execute Disable Bit
- +Physical Address Extension
Specifications
- ~Codename: Prestonia → Nocona
- ~Base clock: 2.40 GHz → 2.80 GHz
- ~Cache: 512 KB L2 Cache → 1 MB L2 Cache
- ~Bus: 533 MHz → 800 MHz
- ~TDP: 65 W → 55 W
- ~Transistors: 55 million → 125 million
- ~Die size: 131 mm2 → 112 mm2
- ~Instruction set: 32-bit → 64-bit
Since the previous major (previous generation): Intel Server CPU v0.0.3 (Pentium III - S 1.26 GHz, 512K Cache, 133 MHz FSB)
Breaking changes
- ~Socket changed from PPGA370 to PPGA604
Components
Instruction sets
- +SSE2
Features
- +Intel 64
- +Hyper-Threading
- +Execute Disable Bit
- +Physical Address Extension
Specifications
- ~Codename: Tualatin → Nocona
- ~Microarchitecture: P6 → NetBurst
- ~Base clock: 1.26 GHz → 2.80 GHz
- ~Cache: 512 KB L2 Cache → 1 MB L2 Cache
- ~Bus: 133 MHz → 800 MHz
- ~TDP: 30.4 W → 55 W
- +Transistors: 125 million
- +Die size: 112 mm2
- ~Instruction set: 32-bit → 64-bit
Raw source data
Show all 35 fields
| Field | Value |
|---|---|
| CpuId | 27097 |
| CpuName | 64-bit Intel Xeon Processor LV 2.80 GHz, 1M Cache, 800 MHz FSB |
| BornOnDate | Q2'04 |
| Bus | 800 MHz |
| Cache | 1 MB L2 Cache |
| ClockSpeed | 2.80 GHz |
| CodeNameText | Products formerly Nocona |
| CoreCount | 1 |
| CoreVoltage | 1.1125V-1.2000V |
| DemandBasedSwitching | No |
| DieSize | 112 mm2 |
| ECCMemory | No |
| EM64 | Yes |
| Embedded | Yes |
| ExecuteDisable | Yes |
| FSBParity | Yes |
| HaltState | Yes |
| HyperThreading | Yes |
| InstructionSet | 64-bit |
| Lithography | 90 nm |
| MarketSegment | Server |
| MaxTDP | 55 W |
| PackageSize | 42.5mm x 42.5mm |
| PhysicalAddressExtension | 32-bit |
| ProductGroup | Legacy Intel Xeon Processors |
| ServicingStatus | End of Servicing Lifetime |
| SocketsSupported | PPGA604 |
| SpeedstepTechnology | No |
| StatusCodeText | Discontinued |
| TBTVersion | No |
| TCase | 86°C |
| TransistorCount | 125 million |
| TXT | No |
| VTX | No |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/27097/64bit-intel-xeon-processor-lv-2-80-ghz-1m-cache-800-mhz-fsb.html |