Intel Server CPU v9.1.7-L
Intel Xeon Processor E5-2418L v3
Metadata
| Property | Value |
|---|---|
| Brand | Xeon |
| Intel name | Intel Xeon Processor E5-2418L v3 |
| Processor number | E5-2418LV3 |
| Codename | Haswell |
| Generation | Haswell |
| Microarchitecture | Haswell |
| Performance class | Xeon E5 |
| Segment | Embedded |
| Released | 2015-Q12015 |
| Status | Discontinued |
| Cores | 6 |
| Threads | 12 |
| Base clock | 2.00 GHz |
| Cache | 15 MB |
| Bus | 6.4 GT/s |
| TDP | 50 W |
| Lithography (as published) | 22 nm |
| Max memory | 384 GB |
| Memory channels | 3 |
| PCIe revision | 3.0 |
| PCIe lanes | 24 |
| Max CPUs per system | 2 |
| Instruction set | 64-bit |
| Socket | FCLGA1356LGA1356 |
| Memory | DDR3 800/1066/1333/1600DDR3 |
| Recommended price | $472 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v15.0.0(22 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.4.1(SSE4.2) - simd: Intel SIMD
v2.0.0(AVX)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
- Foreshadow / L1 Terminal Fault (CVE-2018-3615, CVE-2018-3620, CVE-2018-3646): Speculative reads from the L1 data cache through non-present page table entries, breaking SGX, OS and VMM isolation.
- Microarchitectural Data Sampling (ZombieLoad, RIDL, Fallout) (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091): Data in store buffers, fill buffers and load ports leaks across privilege boundaries.
- Special Register Buffer Data Sampling (CrossTalk) (CVE-2020-0543): RDRAND/RDSEED results leak across cores through a shared staging buffer.
- Retbleed (CVE-2022-29901): Return instructions are hijacked through the branch target buffer on cores without enhanced IBRS.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel Server CPU v9.1.6-L (Xeon E5-2408L v3)
Specifications
- ~Cores: 4 → 6
- ~Threads: 8 → 12
- ~Base clock: 1.80 GHz → 2.00 GHz
- ~Cache: 10 MB → 15 MB
- ~TDP: 45 W → 50 W
- ~Recommended price: $256 → $472
Since the previous minor (lower performance class): Intel Server CPU v9.0.7 (Xeon E3-1245 v3)
Breaking changes
- ~Socket changed from FCLGA1150 to FCLGA1356
- −Removed AVX2 instructions
- −Removed TSX-NI
Components
Instruction sets
- −AVX2
Features
- +Physical Address Extension
- +Demand Based Switching
- −Turbo Boost 2.0
- −TSX-NI
- −Identity Protection Technology
- −Quick Sync Video
- −vPro
Specifications
- ~Cores: 4 → 6
- ~Threads: 8 → 12
- ~Base clock: 3.40 GHz → 2.00 GHz
- ~Cache: 8 MB Intel Smart Cache → 15 MB
- ~Bus: 5 GT/s → 6.4 GT/s
- ~TDP: 84 W → 50 W
- ~Max memory: 32 GB → 384 GB
- ~Memory channels: 2 → 3
- ~PCIe lanes: 16 → 24
- ~Max CPUs per system: 1 → 2
- ~Recommended price: $276 → $472
- −Max clock: 3.80 GHz
- −Graphics max clock: 1.20 GHz
Since the previous major (previous generation): Intel Server CPU v8.1.7 (Xeon E5-2420 v2)
Security
- !Introduced: Special Register Buffer Data Sampling (CrossTalk)
- !Introduced: Retbleed
Features
- −Turbo Boost 2.0
Specifications
- ~Codename: Ivy Bridge EN → Haswell
- ~Microarchitecture: Ivy Bridge → Haswell
- ~Base clock: 2.20 GHz → 2.00 GHz
- ~Cache: 15 MB Intel Smart Cache → 15 MB
- ~Bus: 7.2 GT/s → 6.4 GT/s
- ~TDP: 80 W → 50 W
- ~Recommended price: $406 → $472
- −Max clock: 2.70 GHz
Raw source data
Show all 55 fields
| Field | Value |
|---|---|
| CpuId | 84315 |
| CpuName | Intel Xeon Processor E5-2418L v3 |
| AESTech | Yes |
| BornOnDate | Q1'15 |
| Bus | 6.4 GT/s |
| BusNumPorts | 1 |
| Cache | 15 MB |
| CertifiedUseConditions | Communications Commercial Temp |
| ClockSpeed | 2.00 GHz |
| CodeNameText | Products formerly Haswell |
| CoreCount | 6 |
| DemandBasedSwitching | Yes |
| ECCMemory | Yes |
| EM64 | Yes |
| Embedded | Yes |
| ESUDate | Friday. December 31. 2021 |
| ExecuteDisable | Yes |
| ExtendedPageTables | Yes |
| FlexMemoryTechnology | No |
| HaltState | Yes |
| HyperThreading | Yes |
| IdentityProtectionTechVersion | No |
| InstructionSet | 64-bit |
| InstructionSetExtensions | Intel AVX |
| Lithography | 22 nm |
| MarketSegment | Embedded |
| MaxCPUs | 2 |
| MaxMem | 384 GB |
| MaxMemoryBandwidth | 51.2 GB/s |
| MaxTDP | 50 W |
| MemoryTypes | DDR3 800/1066/1333/1600 |
| NumMemoryChannels | 3 |
| NumPCIExpressPorts | 24 |
| OSGuardTechVersion | Yes |
| PackageSize | 42.5mmx45mm |
| PCIExpressConfigs | x4. x8. x16 |
| PCIExpressRevision | 3.0 |
| PhysicalAddressExtension | 46-bit |
| ProcessorNumber | E5-2418LV3 |
| ProductGroup | Intel Xeon Processor E5 v3 Family |
| ScalableSockets | 2S |
| SecureKeyTechVersion | Yes |
| ServicingStatus | End of Servicing Updates |
| SocketsSupported | FCLGA1356 |
| SpeedstepTechnology | Yes |
| StatusCodeText | Discontinued |
| TBTVersion | No |
| TCase | 93 |
| ThermalMonitoring2Indicator | Yes |
| ThreadCount | 12 |
| TransactionalSynchronizationExtensionVersion | No |
| TXT | Yes |
| VTD | Yes |
| VTX | Yes |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/84315/intel-xeon-processor-e52418l-v3-15m-cache-2-00-ghz.html |