Intel SIMD `v1.2.0`

SSE3

major

1

SSE

minor

2

SSE3

patch

0

SSE3

suffix

—

No suffix

Metadata

Property	Value
Name	SSE3
Introduced	2004
First implemented by	Pentium 4 (Prescott)
Operations	+ horizontal operations
Source	Curated (simd.json)

Uses (dependencies)

simd: Intel SIMD v1.1.0 (SSE2)

Used by (15)

Intel CPU (2)

v9.0.0 Celeron 1.66 GHz, 1M Cache, 667 MHz FSB
v9.0.1 Celeron 1.83 GHz, 1M Cache, 667 MHz FSB

Intel Mobile CPU (5)

v3.0.0 Celeron M ULV 423
v3.0.1 Celeron M 440
v3.1.0 Pentium T2060
v3.1.1 Pentium T2080
v3.1.2 Pentium T2130

Intel Low-power CPU (4)

v1.0.19 Atom Z650
v2.0.8 Atom Z2420
v2.0.9 Atom Z2460
v2.0.10 Atom Z2480

Intel Server CPU (3)

v2.0.0 Xeon LV 1.66 GHz, 2M Cache, 667 MHz FSB
v2.0.1 Xeon LV 2.00 GHz, 2M Cache, 667 MHz FSB
v2.0.2 Xeon LV 2.16 GHz, 2M Cache, 667 MHz FSB

Intel SIMD (1)

v1.3.0 SSSE3

Changelog

Since the previous minor (lower performance class): Intel SIMD `v1.1.0` (SSE2)

Components

~SIMD v1.0.0 (SSE) → SIMD v1.1.0 (SSE2)

Specifications

~First implemented by: Pentium 4 (Willamette) → Pentium 4 (Prescott)
~Operations: + packed doubles and integers → + horizontal operations
−Registers: 8 × 128-bit XMM (16 in 64-bit mode)

Since the previous major (previous generation): Intel SIMD `v0.0.1` (MMX)

Components

+SIMD v1.1.0 (SSE2)

Specifications

~First implemented by: Pentium MMX (P55C) → Pentium 4 (Prescott)
~Operations: packed integers → + horizontal operations
−Registers: 8 × 64-bit (aliased to x87)