Intel CPU v6.0.2
Intel Pentium MMX
Metadata
| Property | Value |
|---|---|
| Brand | Pentium |
| Intel name | Intel Pentium MMX |
| Codename | P55C |
| Generation | P5 (Pentium) |
| Microarchitecture | P5 (superscalar) |
| Performance class | Pentium |
| Released | 1997-011997 |
| Data width | 32-bit |
| Address width | 32-bit |
| Base clock | 166 MHz |
| Max clock | 233 MHz |
| Cache | 32 KB L1 |
| Transistors | 4,500,000 |
| Socket | Socket 7 |
| Instruction sets | |
| Features | |
| Source | Curated (historical-cpus.json) |
Uses (dependencies)
- lithography: Intel Lithography
v7.0.0(350 nm) - simd: Intel SIMD
v0.0.1(MMX)
Used by (0)
Nothing depends on this version.
Changelog
Since the previous patch: Intel CPU v6.0.1 (Pentium (P54C))
Instruction sets
- +MMX
Specifications
- ~Codename: P54C → P55C
- ~Base clock: 75 MHz → 166 MHz
- ~Max clock: 200 MHz → 233 MHz
- ~Cache: 16 KB L1 → 32 KB L1
- ~Transistors: 3,200,000 → 4,500,000
Since the previous major (previous generation): Intel CPU v5.0.0 (486SX)
Breaking changes
- ~Socket changed from Socket 1 to Socket 7
Instruction sets
- +MMX
Features
- +On-die x87 FPU
- +Superscalar (dual pipeline)
- +64-bit data bus
- +Clock multiplier
- +On-die APIC
Specifications
- +Codename: P55C
- ~Microarchitecture: i486 (pipelined, on-die FPU) → P5 (superscalar)
- ~Base clock: 16 MHz → 166 MHz
- ~Max clock: 33 MHz → 233 MHz
- ~Cache: 8 KB L1 → 32 KB L1
- ~Transistors: 1,185,000 → 4,500,000