Intel CPU v7.0.0
Intel Celeron (Covington)
Metadata
| Property | Value |
|---|---|
| Brand | Celeron |
| Intel name | Intel Celeron (Covington) |
| Codename | Covington |
| Generation | P6 (Pentium Pro/II/III) |
| Microarchitecture | P6 (out-of-order) |
| Performance class | Celeron |
| Released | 1998-041998 |
| Data width | 32-bit |
| Address width | 36-bit |
| Base clock | 266 MHz |
| Max clock | 300 MHz |
| Cache | 32 KB L1, no L2 |
| Transistors | 7,500,000 |
| Socket | Slot 1 |
| Instruction sets | |
| Features | |
| Source | Curated (historical-cpus.json) |
Uses (dependencies)
- lithography: Intel Lithography
v8.0.0(250 nm) - simd: Intel SIMD
v0.0.1(MMX)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
Matched by codename; individual steppings may differ.
Changelog
Since the previous major (previous generation): Intel CPU v6.0.0 (Pentium (P5))
Breaking changes
- ~Socket changed from Socket 4 to Slot 1
Security
- !Introduced: Meltdown
- !Introduced: Spectre variant 1 (bounds check bypass)
Instruction sets
- +MMX
Features
- +Out-of-order execution
- +Physical Address Extension
- −Superscalar (dual pipeline)
- −64-bit data bus
Specifications
- ~Codename: P5 → Covington
- ~Microarchitecture: P5 (superscalar) → P6 (out-of-order)
- ~Address width: 32-bit → 36-bit
- ~Base clock: 60 MHz → 266 MHz
- ~Max clock: 66 MHz → 300 MHz
- ~Cache: 16 KB L1 → 32 KB L1, no L2
- ~Transistors: 3,100,000 → 7,500,000