Intel CPU v7.1.1
Intel Pentium II (Klamath)
Metadata
| Property | Value |
|---|---|
| Brand | Pentium |
| Intel name | Intel Pentium II (Klamath) |
| Codename | Klamath |
| Generation | P6 (Pentium Pro/II/III) |
| Microarchitecture | P6 (out-of-order) |
| Performance class | Pentium |
| Released | 1997-051997 |
| Data width | 32-bit |
| Address width | 36-bit |
| Base clock | 233 MHz |
| Max clock | 300 MHz |
| Cache | 32 KB L1, 512 KB L2 (cartridge) |
| Transistors | 7,500,000 |
| Socket | Slot 1 |
| Instruction sets | |
| Features | |
| Source | Curated (historical-cpus.json) |
Uses (dependencies)
- lithography: Intel Lithography
v7.0.0(350 nm) - simd: Intel SIMD
v0.0.1(MMX)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel CPU v7.1.0 (Pentium Pro)
Breaking changes
- ~Socket changed from Socket 8 to Slot 1
- −Removed SSE instructions
Security
- !Introduced: Meltdown
Components
Instruction sets
- −SSE
Specifications
- ~Codename: P6 → Klamath
- ~Base clock: 150 MHz → 233 MHz
- ~Max clock: 200 MHz → 300 MHz
- ~Cache: 16 KB L1, 256 KB–1 MB L2 (in package) → 32 KB L1, 512 KB L2 (cartridge)
- ~Transistors: 5,500,000 → 7,500,000
Since the previous minor (lower performance class): Intel CPU v7.0.1 (Celeron 300 MHz, 128K Cache, 66 MHz FSB)
Breaking changes
- ~Socket changed from SEPP242. PPGA370. SEPP540 to Slot 1
- −Removed SSE instructions
Instruction sets
- −SSE
Features
- +Protected mode
- +Memory management unit
- +32-bit (IA-32)
- +Paging
- +Virtual 8086 mode
- +On-die L1 cache
- +On-die x87 FPU
- +Out-of-order execution
Specifications
- ~Codename: Mendocino → Klamath
- +Data width: 32-bit
- +Address width: 36-bit
- ~Base clock: 300 MHz → 233 MHz
- +Max clock: 300 MHz
- ~Cache: 128 KB L2 Cache → 32 KB L1, 512 KB L2 (cartridge)
- ~Transistors: 19 million → 7,500,000
- −Cores: 1
- −Bus: 66 MHz
- −TDP: 17.8 W
- −Die size: 154 mm2
- −Instruction set: 32-bit
Since the previous major (previous generation): Intel CPU v6.0.1 (Pentium (P54C))
Breaking changes
- ~Socket changed from Socket 7 to Slot 1
Security
- !Introduced: Meltdown
- !Introduced: Spectre variant 1 (bounds check bypass)
Instruction sets
- +MMX
Features
- +Out-of-order execution
- +Physical Address Extension
- −Superscalar (dual pipeline)
- −64-bit data bus
- −Clock multiplier
- −On-die APIC
Specifications
- ~Codename: P54C → Klamath
- ~Microarchitecture: P5 (superscalar) → P6 (out-of-order)
- ~Address width: 32-bit → 36-bit
- ~Base clock: 75 MHz → 233 MHz
- ~Max clock: 200 MHz → 300 MHz
- ~Cache: 16 KB L1 → 32 KB L1, 512 KB L2 (cartridge)
- ~Transistors: 3,200,000 → 7,500,000