Intel Mobile CPU v4.0.0
Intel Celeron M Processor 520
Benchmarks
Total score 683 / 10,000, rank 2104 of 2125.
Every score is out of 10,000, relative to the best CPUs. The total also counts the recommended price ($134, Wikipedia: List of Intel Celeron processors (launch price)); see how scores work.
| Category | Score | Measured | |
|---|---|---|---|
| Single-thread | 809 | 505 points | |
| Multi-thread | 14 | 239 points | |
| 3D renderingestimated | 7 | ||
| Gamingestimated | 463 |
Sources: PassMark (Intel Celeron M 520 @ 1.60GHz, 68 samples)
Metadata
| Property | Value |
|---|---|
| Brand | Celeron |
| Intel name | Intel Celeron M Processor 520 |
| Processor number | 520 |
| Codename | Merom |
| Generation | Core 2 (65 nm) |
| Microarchitecture | Core |
| Performance class | Celeron |
| Segment | Mobile |
| Released | 2007-Q12007 |
| Status | Discontinued |
| Cores | 1 |
| Base clock | 1.60 GHz |
| Cache | 1 MB L2 Cache |
| Bus | 533 MHz |
| TDP | 30 W |
| Lithography (as published) | 65 nm |
| Transistors | 291 million |
| Die size | 143 mm2 |
| Instruction set | 64-bit |
| Socket | PPGA478PGA478 |
| Recommended price | $134 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v12.0.0(65 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.3.0(SSSE3)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
Matched by codename; individual steppings may differ.
Changelog
Since the previous major (previous generation): Intel Mobile CPU v3.0.0 (Celeron M ULV 423)
Breaking changes
- ~Socket changed from PBGA479 to PPGA478
Components
Instruction sets
- +SSSE3
Features
- +Intel 64
- −Physical Address Extension
Specifications
- ~Codename: Yonah → Merom
- ~Microarchitecture: Enhanced Pentium M (Yonah) → Core
- ~Base clock: 1.06 GHz → 1.60 GHz
- ~TDP: 5.5 W → 30 W
- ~Transistors: 151 million → 291 million
- ~Die size: 90 mm2 → 143 mm2
- ~Instruction set: 32-bit → 64-bit
- ~Recommended price: $161 → $134
Raw source data
Show all 35 fields
| Field | Value |
|---|---|
| CpuId | 27977 |
| CpuName | Intel Celeron M Processor 520 |
| BornOnDate | Q1'07 |
| Bus | 533 MHz |
| Cache | 1 MB L2 Cache |
| ClockSpeed | 1.60 GHz |
| CodeNameText | Products formerly Merom |
| CoreCount | 1 |
| CoreVoltage | 0.95V-1.30V |
| DemandBasedSwitching | No |
| DieSize | 143 mm2 |
| EM64 | Yes |
| Embedded | No |
| ExecuteDisable | Yes |
| FSBParity | No |
| HaltState | No |
| HyperThreading | No |
| InstructionSet | 64-bit |
| Lithography | 65 nm |
| MarketSegment | Mobile |
| MaxTDP | 30 W |
| PackageSize | 35mm x 35mm |
| ProcessorNumber | 520 |
| ProductGroup | Legacy Intel Celeron Processor |
| ServicingStatus | End of Servicing Lifetime |
| SocketsSupported | PPGA478 |
| SpeedstepTechnology | No |
| StatusCodeText | Discontinued |
| TBTVersion | No |
| TCase | 100°C |
| ThermalJunctionRateCode | 100°C |
| TransistorCount | 291 million |
| TXT | No |
| VTX | No |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/27977/intel-celeron-m-processor-520-1m-cache-1-60-ghz-533-mhz-fsb.html |