Intel Mobile CPU v5.3.11
Intel Core2 Duo Processor T6400
Benchmarks
Total score 910 / 10,000, rank 2003 of 2125.
Every score is out of 10,000, relative to the best CPUs. The total also counts the recommended price (unknown for this CPU, counted as average); see how scores work.
| Category | Score | Measured | |
|---|---|---|---|
| Single-thread | 1,295 | 797 points | |
| Multi-thread | 43 | 747 points | |
| 3D renderingestimated | 24 | ||
| Gamingestimated | 907 |
Sources: PassMark (Intel Core2 Duo T6400 @ 2.00GHz, 858 samples)
Metadata
| Property | Value |
|---|---|
| Brand | Core 2 |
| Intel name | Intel Core2 Duo Processor T6400 |
| Processor number | T6400 |
| Codename | Penryn |
| Generation | Core 2 (45 nm) |
| Microarchitecture | Penryn |
| Performance class | Core 2 Duo |
| Segment | Mobile |
| Released | 2009-Q12009 |
| Status | Discontinued |
| Cores | 2 |
| Base clock | 2.00 GHz |
| Cache | 2 MB L2 Cache |
| Bus | 800 MHz |
| TDP | 35 W |
| Lithography (as published) | 45 nm |
| Transistors | 410 million |
| Die size | 107 mm2 |
| Instruction set | 64-bit |
| Socket | PGA478 |
| Instruction sets | |
| Features | |
| Source | Intel ARK (via cpu-spec-dataset) |
Uses (dependencies)
- lithography: Intel Lithography
v13.0.0(45 nm) - simd: Intel SIMD
v0.0.1(MMX) - simd: Intel SIMD
v1.4.0(SSE4.1)
Used by (0)
Nothing depends on this version.
Known vulnerabilities and defects
- Meltdown (CVE-2017-5754): Rogue data cache load: user code can read kernel memory through speculative execution.
- Spectre variant 1 (bounds check bypass) (CVE-2017-5753): Mistrained conditional branches speculatively read out-of-bounds data. Mitigated in software only; every speculative out-of-order core is affected.
Matched by codename; individual steppings may differ.
Changelog
Since the previous patch: Intel Mobile CPU v5.3.10 (Core2 Duo SU9600)
Breaking changes
- ~Socket changed from BGA956 to PGA478
- −Removed VT-x
Features
- −VT-x
- −Trusted Execution Technology
Specifications
- ~Base clock: 1.60 GHz → 2.00 GHz
- ~Cache: 3 MB L2 Cache → 2 MB L2 Cache
- ~TDP: 10 W → 35 W
- −Recommended price: $289
Since the previous minor (lower performance class): Intel Mobile CPU v5.2.0 (Core2 Solo ULV SU3500)
Breaking changes
- ~Socket changed from BGA956 to PGA478
- −Removed VT-x
Features
- −VT-x
- −Trusted Execution Technology
Specifications
- ~Cores: 1 → 2
- ~Base clock: 1.40 GHz → 2.00 GHz
- ~Cache: 3 MB L2 Cache → 2 MB L2 Cache
- ~TDP: 5.5 W → 35 W
- −Recommended price: $262
Since the previous major (previous generation): Intel Mobile CPU v4.1.3 (Pentium T3400)
Performance
- ~Total score 850 → 910 (+7%)
- ~Single-thread 1189 → 1295 (+9%)
- ~Multi-thread 38 → 43 (+13%)
- ~3D rendering 21 → 24 (+14%)
- ~Gaming 824 → 907 (+10%)
Components
Instruction sets
- +SSE4.1
Specifications
- ~Codename: Merom → Penryn
- ~Microarchitecture: Core → Penryn
- ~Base clock: 2.16 GHz → 2.00 GHz
- ~Cache: 1 MB L2 Cache → 2 MB L2 Cache
- ~Bus: 667 MHz → 800 MHz
- ~Transistors: 291 million → 410 million
- ~Die size: 143 mm2 → 107 mm2
Raw source data
Show all 32 fields
| Field | Value |
|---|---|
| CpuId | 40479 |
| CpuName | Intel Core2 Duo Processor T6400 |
| BornOnDate | Q1'09 |
| Bus | 800 MHz |
| Cache | 2 MB L2 Cache |
| ClockSpeed | 2.00 GHz |
| CodeNameText | Products formerly Penryn |
| CoreCount | 2 |
| CoreVoltage | 1.000V-1.250V |
| DemandBasedSwitching | No |
| DieSize | 107 mm2 |
| EM64 | Yes |
| Embedded | No |
| ExecuteDisable | Yes |
| HyperThreading | No |
| InstructionSet | 64-bit |
| Lithography | 45 nm |
| MarketSegment | Mobile |
| MaxTDP | 35 W |
| PackageSize | 35mm x 35mm |
| ProcessorNumber | T6400 |
| ProductGroup | Legacy Intel Core Processors |
| ServicingStatus | End of Servicing Updates |
| SocketsSupported | PGA478 |
| SpeedstepTechnology | Yes |
| StatusCodeText | Discontinued |
| TBTVersion | No |
| ThermalJunctionRateCode | 105°C |
| TransistorCount | 410 million |
| TXT | No |
| VTX | No |
| SourceUrl | https://ark.intel.com/content/www/us/en/ark/products/40479/intel-core2-duo-processor-t6400-2m-cache-2-00-ghz-800-mhz-fsb.html |