Intel SIMD `v1.4.0`

SSE4.1

major

1

SSE

minor

4

SSE4

patch

0

SSE4.1

suffix

—

No suffix

Metadata

Property	Value
Name	SSE4.1
Introduced	2008
First implemented by	Core 2 (Penryn)
Operations	+ dot product, blend, rounding
Source	Curated (simd.json)

Uses (dependencies)

simd: Intel SIMD v1.3.0 (SSSE3)

Used by (109)

Intel CPU (24)

v11.0.0 Celeron E3200
v11.0.1 Celeron E3300
v11.0.2 Celeron E3400
v11.1.0 Pentium E5200
v11.1.1 Pentium E5300
v11.1.2 Pentium E5400
v11.1.3 Pentium E5500
v11.1.4 Pentium E5700
v11.1.5 Pentium E5800
v11.1.6 Pentium E6300
v11.1.7 Pentium E6500
v11.1.7-K Pentium E6500K
v11.1.8 Pentium E6600
v11.1.9 Pentium E6700
v11.2.0 Core2 Duo E7500
v11.2.1 Core2 Duo E7600
v11.3.0-S Core2 Quad Q8200S
v11.3.1 Core2 Quad Q8300
v11.3.2 Core2 Quad Q8400
v11.3.2-S Core2 Quad Q8400S
v11.3.3-S Core2 Quad Q9400S
v11.3.4 Core2 Quad Q9505
v11.3.4-S Core2 Quad Q9505S
v11.3.5-S Core2 Quad Q9550S

Intel Mobile CPU (39)

Intel Server CPU (45)

Intel SIMD (1)

v1.4.1 SSE4.2

Changelog

Since the previous minor (lower performance class): Intel SIMD `v1.3.0` (SSSE3)

Components

~SIMD v1.2.0 (SSE3) → SIMD v1.3.0 (SSSE3)

Specifications

~First implemented by: Core 2 (Merom/Conroe) → Core 2 (Penryn)
~Operations: + shuffle, absolute value, sign → + dot product, blend, rounding

Since the previous major (previous generation): Intel SIMD `v0.0.1` (MMX)

Components

+SIMD v1.3.0 (SSSE3)

Specifications

~First implemented by: Pentium MMX (P55C) → Core 2 (Penryn)
~Operations: packed integers → + dot product, blend, rounding
−Registers: 8 × 64-bit (aliased to x87)