Intel SIMD `v2.3.0`

AVX10.1

major

2

AVX

minor

3

AVX10

patch

0

AVX10.1

suffix

—

No suffix

Metadata

Property	Value
Name	AVX10.1
Introduced	2024
First implemented by	Xeon 6 (Granite Rapids)
Operations	converged AVX-512 feature set with versioned enumeration
Source	Curated (simd.json)

Uses (dependencies)

simd: Intel SIMD v2.2.0 (AVX-512)

Used by (6)

Intel Server CPU (5)

v20.1.0-P Xeon 6952P
v20.1.1-P Xeon 6960P
v20.1.2-P Xeon 6972P
v20.1.3-P Xeon 6979P
v20.1.4-P Xeon 6980P

Intel SIMD (1)

v2.3.1 AVX10.2

Changelog

Since the previous minor (lower performance class): Intel SIMD `v2.2.0` (AVX-512)

Components

~SIMD v2.1.0 (AVX2) → SIMD v2.2.0 (AVX-512)

Specifications

~First implemented by: Xeon Phi (Knights Landing), Skylake-SP → Xeon 6 (Granite Rapids)
~Operations: 512-bit vectors, EVEX encoding → converged AVX-512 feature set with versioned enumeration
−Registers: 32 × 512-bit ZMM, 8 mask registers

Since the previous major (previous generation): Intel SIMD `v1.3.0` (SSSE3)

Components

~SIMD v1.2.0 (SSE3) → SIMD v2.2.0 (AVX-512)

Specifications

~First implemented by: Core 2 (Merom/Conroe) → Xeon 6 (Granite Rapids)
~Operations: + shuffle, absolute value, sign → converged AVX-512 feature set with versioned enumeration