Intel SIMD v2.3.1
AVX10.2
major
2
AVX
minor
3
AVX10
patch
1
AVX10.2
suffix
—
No suffix
Metadata
| Property | Value |
|---|---|
| Name | AVX10.2 |
| Introduced | 2025 |
| First implemented by | Diamond Rapids (announced) |
| Operations | + 256-bit embedded rounding, new conversions |
| Source | Curated (simd.json) |
Uses (dependencies)
- simd: Intel SIMD
v2.3.0(AVX10.1)
Used by (0)
Nothing depends on this version.
Changelog
Since the previous patch: Intel SIMD v2.3.0 (AVX10.1)
Specifications
- ~First implemented by: Xeon 6 (Granite Rapids) → Diamond Rapids (announced)
- ~Operations: converged AVX-512 feature set with versioned enumeration → + 256-bit embedded rounding, new conversions
Since the previous minor (lower performance class): Intel SIMD v2.2.0 (AVX-512)
Components
Specifications
- ~First implemented by: Xeon Phi (Knights Landing), Skylake-SP → Diamond Rapids (announced)
- ~Operations: 512-bit vectors, EVEX encoding → + 256-bit embedded rounding, new conversions
- −Registers: 32 × 512-bit ZMM, 8 mask registers
Since the previous major (previous generation): Intel SIMD v1.3.0 (SSSE3)
Components
Specifications
- ~First implemented by: Core 2 (Merom/Conroe) → Diamond Rapids (announced)
- ~Operations: + shuffle, absolute value, sign → + 256-bit embedded rounding, new conversions